System-on-a-Chip (SOC) integrated circuits composed of embedded cores are now commonplace. Nevertheless, there remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design and manufacturing capabilities. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols. In addition, long interconnects, high density, and high-speed designs lead to new types of faults involving crosstalk and signal integrity. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation is an edited work containing thirteen contributions that address various aspects of SOC testing. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation is a valuable reference for researchers and students interested in various aspects of SOC testing.MATLAB Usera#39;s and Reference Manual, 2000 The MathWorks, Inc., Version 6.0. 0.88, 2000. 31. MOSISOrganization ... Design Automation Conf (DACa#39;01), June 2001, pp. 792a797. 36. ... U. Sparmann, H. Muller, and S. Reddy, aUniversal Delay Test Sets for Logic Networks, a IEEE Trans on VLSI Systems, vol. 7, no. 2, pp.
Title | : | SOC (System-on-a-Chip) Testing for Plug and Play Test Automation |
Author | : | Krishnendu Chakrabarty |
Publisher | : | Springer Science & Business Media - 2013-04-17 |
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